1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor substrate and an inspection method therefor, which are particularly suitable for semiconductor substrates used in memory devices and logic devices having MOS structures.
2. Description of the Background Art
Silicon wafers mainly used to make up substrates of semiconductor devices are CZ silicon substrates cut out from a single crystal silicon made by the Czochralski (CZ) method. Additionally widely used are substrates (epitaxial wafers) made by forming a single crystal Si layer (epitaxial layer) on a CZ silicon substrate by vapor phase epitaxial growth.
It is known by an evaluation of dielectric breakdown of an oxide film of a capacitor made on a silicon substrate that oxygen precipitations (BMD: Bulk Micro Defect) resulting from precipitation of oxygen contained in a CZ silicon substrate causes degradation of characteristics. However, in the epitaxial layer of an epitaxial wafer, no oxygen enters into the epitaxially grown layer from vapor phase, and the epitaxial layer contains only interstitial oxygen that diffuses from the CZ silicon substrate during epitaxial growth process. Therefore, its oxygen concentration is very low, and degradation in integrity of the gate oxide film seldom occurs.
Apart from this, epitaxial wafers have other advantages. For example, since the conductive type of an epitaxial layer made on the substrate can be made different from the conductive type of the substrate, a circuit made thereon can be more easily designed to prevent latch-up. Especially, p-on-p.sup.- wafers having a p.sup.- type layer on a p.sup.+ -type substrate are advantageous in improvement of soft error resistance, gettering function of metal impurities by boron in the p.sup.+ -type region, and so forth, and they are ideal substrates of high-integrated semiconductor devices. When a trench capacitor formed in a substrate is used as a memory cell of a DRAM device, an amount of electric charge over certain level must be held in the capacitor. By using the p.sup.+ -type substrates, expansion of the depletion layer around the trench capacitor can be suppressed, and a necessary amount of electric charge can be held easily.
From the structural viewpoint, p-on-p.sup.- wafers or n-on-p.sup.+ wafers are suitable for use as substrates of high-integrated devices. However, they involve problems derived from their conductive type being p.sup.+. It is already known that precipitation of interstitial oxygen is liable to increase rapidly as the boron concentration in the silicon substrate increases (especially 10.sup.18 atoms/cm.sup.3 or more).
FIG. 14 is a graph showing changes in BMD density depending upon the boron concentration after annealing silicon wafers at 600.degree. C. for three hours and at 1000.degree. C. for 16 hours. It is known that the BMD density rapidly increases from boron concentrations around 10.sup.18 atoms/cm.sup.3.
In case of the above-mentioned DRAM having the trench capacitor structure, since the trench capacitor is made in the p.sup.+ -type region, deterioration in strength of dielectric breakdown of the trench capacitor and other adverse affection to the device characteristics by highly dense BMD are expected.
Also in devices without the trench structure, if the PN junction extends to the BMD generating substrate portion, an increase in leak current and other deterioration in the PN junction occur. The depth of the active layer is relatively shallow in devices without the trench structure. Epi-wafers having p-on-p.sup.+ structures, for example, can be made to keep the deep PN junction off the substrate by increasing the thickness of the epi-layer. However, the thickness of the epi-layer can be increased only to a limited amount in more miniaturized devices because the wafers must be highly plane but the flatness is degraded due to non-uniformity in thickness of the epi-layer as the epi-layer becomes thicker.
Explained below are a prior art technique and its technical knowledge for overcoming the problem.
The CZ method is a method to grow single crystal silicon using molten silicon as a material in a quartz crucible and a seed crystal of single crystal silicon. Oxygen enters into the silicon solution from the crucible and the atmosphere, and is taken into the single crystal silicon during solidifying. Therefore, the silicon crystalline silicon cooled to the room temperature contains an amount of oxygen beyond the solid-soluble limit. Oxygen in the single crystal silicon exists between silicon lattices. By heating the single crystal silicon at a relatively low temperature around or below 800.degree. C., oxygen beyond the solid-soluble limit deposits in the silicon crystal and forms oxygen embryos made up from silicon and oxygen. The precipitation speed depends on the degree of super saturation and the oxygen diffusion speed. The degree of super saturation increases with a decrease in temperature, and the oxygen diffusion speeds increases with an increase in temperature. Therefore, annealing at a temperature approx. 600 to 800.degree. C. (low-temperature annealing) is most liable to produce precipitation embryos. The size of each precipitation embryo is very small and is estimated to be 1 nm or less. The oxygen precipitation embryos grow large due to aggregation of oxygen around the precipitation embryo when annealed at a temperature around 1000.degree. C. (medium-temperature annealing) and form oxygen precipitations (BMD). The grown oxygen precipitations (BMD) can be readily observed by an electron microscope, infrared scattering method, selective etching method, and so on.
Whether an oxygen embryo grows or contracts during low-temperature or medium temperature annealing depends on the size of the precipitated oxygen embryo and the oxygen concentration in the semiconductor substrate as already known. Oxygen embryos larger than a given size grow by annealing, but oxygen embryos smaller than a given size contract by annealing. The critical size of oxygen embryos between growth and contraction increases as the oxygen concentration in the semiconductor substrate becomes lower.
Since the density of oxygen precipitations increases with an increase in concentration of interstitial oxygen and with an increase in time of the low-temperature annealing and time of the subsequent medium-temperature annealing, the interstitial oxygen concentration in the surface layer must be decreased to form a non-defective layer (DZ: Denuded Zone) in the region for making the device up to the depth around 10 .mu.m from the surface
In order to make DZ in the device-forming region, typically used is a method of reducing the oxygen concentration in the silicon surface layer by annealing the wafer at a high temperature in a non-oxide atmosphere to externally disperse interstitial oxygen. In this case, the higher the temperature, the more effective the external dispersion of oxygen, and the temperature around 1200.degree. C. is used.
A problem with high-temperature annealing beyond approximately 1100.degree. C. is the need for a high technology and a high facility investment which inevitably increases the cost of final semiconductor products. Another problem with high-temperature annealing is an adverse affection to device characteristics due to redistribution of boron in a p-on-p.sup.+ epi-wafer annealed at a high temperature.